1. Field of the Invention
The invention relates to a semiconductor device and method for fabricating the same, and more particularly to a semiconductor device with a relatively higher device density and a method for fabricating the same.
2. Description of the Related Art
Three dimensional (3D) integrated circuits (ICs) and fabricating processes thereof are important for circuit density and electronic performances of devices, such as, logic devices or memory devices. Concepts of conventional ICs, however, follow two dimensional (2D) fabricating processes. U.S. Pat. No. 7,005,350 B2 a conventional 3D flash memory array 100 shown in FIG. 1. A first level memory array 1 is formed. The first level memory array 1 mainly comprises a channel stripe 102, an oxide-nitride-oxide (ONO) layer 104, a word line stack 106 and a source/drain region 110. A second level memory array 2 is then formed after forming the first level memory array 1. Elements of the second level memory array 2 are substantially the same as the first level memory array 1. Thus, a formation of the conventional 3D flash memory array 100 is completed. Amount of masking procedures for the conventional 3D flash memory array, however, are increased due to memory array lamination. The memory array lamination of the conventional 3D flash memory array 100 is performed by repeatedly laminating the first level memory array 1. Fabricating cost of the conventional 3D flash memory array 100 can mainly be reduced by saving a substrate area due to each memory array level process has the same fabricating cost. Additionally, gate oxide quality and silicide contact resistance of the first level memory array 1 of the conventional 3D flash memory array 100 may be hindered by thermal budget when forming the upper second level memory array 2; resulting in electronic performances of the first level memory array 1 and the second level memory array 2 to be different. Moreover, the second level memory array 2 channel layer can not be subjected to a high temperature annealing process to achieve higher carrier mobility, for example, higher than 1000° C., due to damage to the first level memory array 1 metal interconnects. Therefore, an additional compensation method is used to keep the same electronic performance of each memory array level for the conventional 3D flash memory array.
Thus, a semiconductor device with higher device density and the same device electronic performances is desirable.